incoming call line identification (iclid) receiver with ring detection integrated circuit systems, inc. ics1660 incoming call line identification (iclid) receiver with ring detection features ? ? ring detection ? ? low battery detection ? ? internal 5v regulator - can externally source 25ma ? ? fsk demodulation ? ? power-down in standby mode ? ? direct interface to host microprocessor or microcomputer applications ? ? telephones ? ? facsimile machines ? ? modems ? ? telephone interface equipment ? ? stand-alone iclid products description the ics1660 ?iclid? circuit is a monolithic cmos vlsi device that decodes and detects the frequency shift keying (fsk) signals used in caller identification telephone service. the ics1660 , when used in conjunction with some external components, amplifies, filters and demodulates the fsk data transmitted from the central office to the telephone subscriber. the ics1660 detects the first power ring signal and demodu- lates the 1200 baud fsk data transmitted during the silent interval between the first and second power ring. the fsk data is transmitted from the central office switch to the subscriber line as part of the class service of calling number delivery (cnd). this data is then demodulated, amplified and filtered by the ics1660 and digitally transmitted to the host control- ler/processor. the ics1660 is designed to be powered by any off-the-shelf 9.0 volt battery. the on-chip 5.0 voltage regulator powers the host microprocessor and any external circuitry supported by the ics1660 . this portion of the circuit can be overridden by connecting the v in pin (18) to the v dd pin (1) for a common power supply. a low battery detection circuit is also provided on-chip and signals the microprocessor on the fsk/bat pin (17) when the pwr pin (16) input is pulled low. to line to phone surge and lightning protection 2 x 16 lcd display ac/dc adapter dc jack keypad external memory (ram/eprom) 8 data 3 control ics1660 rng detect fsk demodulation signal conditioning low battery detect power-down standby voltage regulation 9vdc +5vdc micro- controller iclid block diagram ics1660reva100694 idt? / ics? incoming call line identification (iclid) receiver with ring detection ics1660 1 data sheet ics1660
idt? / ics? incoming call line identification (iclid) receiver with ring detection ics1660 2 ics1660 incoming call line identification (iclid) receiver with ring detection tsd block diagram .022 f f1 f2 f3 .033 f ring fout .0033 f .022 f ampin vcoset lfilter postf 500k .01 f 1000pf fskbat mux pll low battery detect post amp power control regulator 5 volt buffer ring detect diff amp filter pwr 10 f vin vdd vss buffer 0.01 f 0.01 f line af line bf line a line b 82k 0.1 f 0.1 f 82k tip ring 15 10 13 2 11 12 6 4 3 17 16 9 18 1 14 8 7 5 ics1660 2
idt? / ics? incoming call line identification (iclid) receiver with ring detection ics1660 3 ics1660 incoming call line identification (iclid) receiver with ring detection tsd function description power supply the ics1660 is designed to be powered by a standard 9.0 volt battery. the chip contains a voltage regulator that powers external circuitry and provides the supply voltage for all digital i/o on the circuit. this allows easy interface between the ics1660 and other standard logic working at 5.0v. this regu- lator has short circuit protection and requires an external fil- ter/compensation capacitor with a minimum value of 10uf. in the event that an external regulated 5.0v supply is available, the v in and v dd pins can be shorted to permit the entire system to work from a common supply. a low battery detection circuit is provided. this circuit is designed for a typical trip point of 6.0v with hysteresis of about 200mv above the trip point. this signal is low active and is multiplexed to the fskbat output pin when the pwr input is low. in an effort to keep power dissipation to a minimum and extend battery life, most of the analog circuits are turned off when the circuit is at rest waiting for a ring detect, (pwr pin low). during this time only the regulator, low battery detect, refer- ence generator, and ring detect circuits are active. when the pwr pin is high, all circuits are active. ring detect as shown in the attached block diagram, the linea and lineb inputs should be connected to the telephone line through external 82k ? resistors and 0.1uf capacitors. this provides dc isolation and sets up a voltage divider with inter- nal resistors that will detect 35.0v rms typically. this voltage is applied across the linea and lineb inputs. the design value of the internal resistors is 8.1k ? 20% with relative accuracy of 2%. the ring output is high active. differential front end as shown in the attached block diagram, the linea and lineb inputs go into a differential amplifier which in turn drives a filter. all resistors are internal to the chip while capacitors are connected as shown in the block diagram. after filtering, the signal is ac coupled into a high gain amplifier that converts the signal to digital. this digital signal in turn acts as the reference frequency for the phase comparator section of the phase locked loop. fsk demodulation after the signal from the telephone line has been filtered, amplified and converted to digital, it acts as an input to a phase locked loop. this pll does fsk demodulation. the summing amplifier shown in the block diagram provides a signal to the vco that should be about 0.5v for mark frequency (1200 hz), and 2.0v for space frequency (2200 hz). as shown in the block diagram, the lfilter (loop filter) output has a post filter attached to it. this postf signal is sent to a comparator. the other side of the comparator is set to approximately 2.5v. this comparator has a small amount (200mv) of hysteresis and its output is the demodulated fsk data. the fsk output is high for mark frequency and low for space frequency. fsk data is multiplexed out of the fskbat pin when the pwr input is high. the vco frequency is set with one external resistor with a value in the range of 300k for a center frequency of 1700 hz. the lock range will be 660 hz to 2630 hz typical. the center frequency reproducibility will be 15%. the center frequency can be adjusted in the system by connecting ampin to vss, pwr to vdd, and adjusting the external resistor for 1700 hz. this frequency can be observed at the lfilter output or the fsk/bat output. ics1660 3
idt? / ics? incoming call line identification (iclid) receiver with ring detection ics1660 4 ics1660 incoming call line identification (iclid) receiver with ring detection tsd typical application 120vac ac/dc adapter 12vdc 1n4002 x 4 300 9.1v 1n4002 9 v dc 0.1 f 100 f .022 f .033 f .033 f 0.01 f 1000 pf vr1 18 vin 4 lfilter 6 vcoset 3 postf 13 10 filter2 15 filter1 14 line bf 8 line b 0.01 f 250v tip ring 10 ohm mov 82k 82k 0.1 f 250v 0.1 f 250v 0.01 f 250v +5v a b 7 line a 5 line af 16 pwr 17 fsk/bat 2 ring filter out 11 12 amp in 1 vdd 100 f 0.1 f a b 0.0033 f tp1 tp2 0.022 f vout micro control- ler 9 vss cal jumper 5v +/ ? 10% cal jumper ics1660 ics1660 4
pin descriptions pin number name description dip so 1 1 vdd supply voltage pin to external circuits. output of 5.0 volt regulator. 2 2 ring ring detect output signal to the host microprocessor. 3 3 postf post loop filter signal used by demodulator. 4 4 lfilter loop filter for pll. 5 5 lineafilter filter input from line ?a.? 6 6 vcoset center frequency adjustment pin. 7 7 linea ?tip? input from telephone line. 8 8 lineb ?ring? input from telephone line. 9 9 vss ground. 10 11 filter2 active filter pin. 11 12 filterout active filter pin. 12 13 ampin input from active filter. 13 14 filter3 active filter pin. 14 15 linebfilter filter input from line ?b.? 15 16 filter1 active filter pin. 16 17 pwr logic input signal to switch from low current standby mode. 17 18 fsk/bat multiplexed output signal controlled by pwr pin. in standby mode, this is a low battery (active low) signal. during fsk demodulation, this is the data line to the p (mark = high). 18 19 vin input power supply pin. 10 20 nc on soic ics1660 5 idt? / ics? incoming call line identification (iclid) receiver with ring detection ics1660 5 ics1660 incoming call line identification (iclid) receiver with ring detection tsd
idt? / ics? incoming call line identification (iclid) receiver with ring detection ics1660 6 ics1660 incoming call line identification (iclid) receiver with ring detection tsd input/output specifications digital ring and fskbat outputs are standard cmos outputs with voltage swings between v ss and v dd . pwr is a logic input. a level converter circuit is on chip to allow the logic signal that swing between v ss and v dd to be internally converted to signals that swing between v ss and v in . it should be noted that to minimize power consumption caused by through current in logic gates, the pwr input should always swing to within 100 mv of v ss or v dd . the pwr input signal is low when the ics1660 is in lower power mode waiting for an incoming call. the lfilter output is a standard cmos output powered from vdd. this output has an internal resistor with a typical value of 30k ? . this is used in conjunction with the external capacitor shown in the block diagram to form the loop filter for the pll. analog the value of the ring detect is as previously discussed 35.0v rms typical. the actual value is set by the choice of the external resistors that are connected to the linea and lineb inputs. the matching of these resistors to the internal 8.1k ? resistors is also a factor. the signal level at the chip that will cause a ring is the bandgap voltage, (1.25v) or below. the chip is designed for an input signal level of -12.5dbm to -28.5dbm into 900 ohms. this translates to a signal that is between 100 mv and 636 mv peak to peak. the filter section should be connected as shown in the block diagram. using the external capacitors as shown, and assuming nominal values on the internal resistors, the corner frequencies are 900 hz and 3860 hz. an external resistor with a value of approximately 330k ? is connected between the lfilter and postf pads. this resis- tor along with the external capacitor shown in the block dia- gram form the post filter. this post filter is used in conjunction with the comparator to do the fsk demodulation. absolute maximum ratings * (voltages referenced to v ss ) supply voltage . . . . . . . . v in . . . . . . . . . -0.5v to +10v voltage at any input . . . . . . . . . . . . . . . . . -0.5v to v dd + 0.5v operation temperature range . . . . . . . . . . . -55 c to +125 c storage temperature range . . . . . . . . . . . . . -50 c to 150 c * absolute maximum ratings are those values beyond which the safety of this device cannot be guaranteed. these values are not recommended operating conditions. ics1660 6
ics1660 incoming call line identification (iclid) receiver with ring detection tsd dc characteristics v in = 4.5v - 10.0v; t a = 0 c - 70 c, recommended operating range parameter symbol conditions min typ max units standby current i in pwr low, v in =9.0v, i dd =2 a -2030ua active current i in pwr high, v in =9.0v vcoset=300k - - 10 ma regulator output voltage v dd 4.5 5.0 5.5 volts regulator output current i dd output current 2.0 25.0 ma regulator dropout v in 0.5 1.0 volts low battery detect 6.0 volts low battery detect hysteresis low battery detect - hysteresis 200 mv output current sink/source ring source current i out vout h = v dd - 0.5v -500 - - ua fskbat and ring sink current i out vout l = v ss + 0.4v - - 500 ua ordering information ics1660n or ICS1660M example: ics xxxx m package type n=dip ( plastic) m=soic device type (consists of 3 or 4 digit numbers) prefix ics, av=standard device; gsp=genlock device ics1660 7 idt? / ics? incoming call line identification (iclid) receiver with ring detection ics1660 7
ics1660 incoming call line identification (iclid) receiver with ring detection tsd ics1890 auto-negotiation advertisement register (register 4 [0x04]) tsd mk1491-14 opti acpi firestar clock source tsd ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support clockhelp@idt.com 408-284-8200 innovate with idt and accelerate your future networks. contact: www.idt.com ics280 triple pll field prog. spread spectrum clock synthesizer tsd
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